In typical circuit design, circuit components are arranged to optimize space and/or circuit performance. Such arrangements can include the “layout” or pattern definition of each of the layers used in a semiconductor manufacturing process. For example, such layout(s) can include metal interconnect layers or metal connectivity layers that are converted to masks or reticles for use in a wafer fabrication facility that manufactures ICs (i.e., “chips”).
While some circuits are designed using “custom” layout processes, others are designed using a partially or fully automated design flow. Application-Specific Integrated Circuit (ASIC) designs, as well as other functional blocks within a larger chip, such as System-On-Chip (SOC) designs, may employ custom and/or ASIC type flows on the same chip. In any event, typical ASIC flows use “place-and-route” tools for placing logic or circuit “blocks” and then “routing” or connecting the interface signals between the blocks. Such routing between circuit blocks is typically done using one or more metal connectivity layers for each signal path. In most modern ASIC designs, at least five layers of metal connectivity are employed.
Referring now to FIG. 1A, a logical diagram of a typical signal path is shown. A signal path generally has a plurality of circuit blocks (e.g., circuit blocks 101-105) with “nets” or wires 111-114 communicatively coupled between circuit blocks. A signal path generally has flip-flops or other state memory devices at each end of the path (e.g., circuit blocks 101 and 105), with logic gates or other logical operation circuit blocks between the flip-flops (e.g., circuit blocks 102-104). Typically, a signal path is designed and/or required to propagate a signal from a beginning flip-flop 101 to an ending flip-flop 105 during one clock pulse. Therefore, when the circuit blocks and nets of a signal path are placed and routed on an integrated circuit device, the propagation delay of the wires that form the nets must be taken into account.
In conventional place-and-route flows, circuit blocks or “cells” are first placed in desired locations and sized (e.g., had their drive strength adjusted by changing transistor sizes and/or adding buffer stages) in accordance with a projected routing and capacitive load based on these desired cell locations. Then, signals are actually routed between the circuit blocks. A standard cell is a specific design for each gate in the library. With advancements in integrated circuit fabrication processes, the routing area is becoming relatively more important than the total number of transistors used with respect to the overall area of ASIC designs. A modern ASIC design may comprise hundreds of thousands if not millions of cells and wires or nets. Therefore, the majority of ASIC routing is performed automatically and standard cell sizes are generally used to support place-and-route tools. Thus, referring now to FIG. 1B, circuit blocks 101-105 may be placed into cells of integrated circuit layout 120, where the height of each cell in rows R1 through R6 is the same height.
Although nets 111-114 are shown as straight logical interconnections between circuit blocks 101-105, wires are typically placed on horizontal and vertical wire tracks. For example, referring now to FIG. 2A, in integrated circuit layout 200 cells 201 and 202 may be ideally connected by straight path net 210. With most conventional routing tools, in the best case a net between cells 201 and 202 may be routed along a horizontal wiring track to form net portion 211a, then along a horizontal wiring track to form net portion 211b. 
Cells are generally placed in an integrated circuit layout before detailed or “global” routing is performed. The placement is generally based on an estimate of the length of wire that will be necessary to couple the two cells (e.g., based on an approximate length of horizontal and vertical wire track that would be necessary to connect the two cells). However, routing resources may be limited so that when the nets are globally routed it may not be possible to route the net near the ideal path. In some cases, the actual route of the wire will not satisfy timing constraints for the net and/or for a signal path that includes the net. Routing resources are generally limited because wires in each metal layer may have a minimum width for each wire and a minimum spacing between each wire, depending on the manufacturing process limitations and the electrical characteristics of the metal. In addition, there is generally a limit on the number of wire layers available (e.g., typically six to eight metal layers), and some number of metal layers may be reserved for intra-cell routing (e.g., typically the bottom two to three layers).
When all of the routing resources in an area of an integrated circuit layout are used, the region may be referred to as “congested.” No additional wires can be routed through a congested region. In addition, some regions of a layout may not be routed through because they contain hierarchical blocks of cells that are pre-placed and pre-routed. These hierarchical blocks may form memory devices, intellectual property cores licensed from third parties, or any other pre-placed and pre-routed multi-cell circuit blocks. In some cases, these hierarchical blocks may be congested. However, in many cases, the content of a hierarchical block is not known to the layout and routing process and/or software, and is treated as a black box through which one cannot route any wires/signals.
As shown in FIG. 2B, integrated circuit layout 200 may include a hierarchical block region 230 and/or a congested region 231. As a result, net 212 between cells 201 and 202 must be routed around regions 230 and 231, resulting in a path that is longer than was estimated when cells 201 and 202 were initially placed. Given the increasing demands on circuit designers to more quickly create chips of increasing density, decreasing wire and transistor widths, and decreasing power supply and power consumption, it is difficult to ensure that cells are placed so that nets meet timing and/or power requirements after global routing in an automated place-and-route flow. Increasing the complexity, flexibility, and/or functionality of the circuitry on a chip exacerbates these challenges.
Therefore, it is desirable to provide methods for automatically improving the placement of cells to improve routing around congested regions after global routing has been performed without thereby causing timing violations in other signal paths on the same integrated circuit device.
This “Background” section is provided for background information only. The statements in this “Background” are not an admission that the subject matter disclosed in this “Background” section constitutes prior art to the present disclosure, and no part of this “Background” section may be used as an admission that any part of this application, including this “Background” section, constitutes prior art to the present disclosure.